1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device for forming a contact hole and a wiring embedding groove in an interlayer insulation film and then forming a multilayer metal wiring.
2. Description of the Related Art
There is a limit to increasing a two-dimensional wiring region in a semiconductor device. To overcome this limit, a multilayer wiring structure which is a three-dimensional wiring structure has been provided. The multilayer wiring structure requires reducing inter-wiring capacity to thereby decrease an impedance.
A technique for embedding a wiring into an interlayer insulation film is known as one of methods for forming a multilayer wiring. Among those embedded wiring formation techniques, particularly, a so-called dual damascene process (or an interlayer wiring method) for forming a groove for embedding a contact hole and a wiring into an interlayer insulation film, then embedding a conductive material into the contact hole to form a contact and, at the same time, embedding a conductive material into the groove to form a metal wiring is disclosed by, for example, Japanese Patent Application Laid-Open No. 9-306988.
The interlayer wiring formation method includes, first, as shown in FIG. 1A, forming an interlayer insulation film (silicon oxide film) 602 on a conductive material 601, coating a photo resist 604 after growing an interlayer nitride film 603 serving as a stopper and forming a contact hole pattern on the interlayer nitride film 603 by normal photolithography and dry etching. In this case, the contact hole pattern is only formed on the interlayer nitride film 603.
Next, as shown in FIG. 1B, after removing the photo resist 604, an interlayer insulation film (silicon oxide film) 606 is grown.
As shown in FIG. 1C, after the photo resist 607 is coated on the interlayer insulation film 606, a pattern for a wiring groove is formed on the photo resist 607 by photolithography. Using this photo resist 607 as a mask, the interlayer insulation films 606 and 602 are etched under the condition that the etch selectivity of the oxide film to the nitride film is high. By so doing, the interlayer insulation film 606 is etched and a wiring groove 608 is formed. Also, the interlayer insulation film 602 is preferentially etched over the interlayer nitride film 603, so that the interlayer insulation film 602 is etched with the interlayer nitride film 603 used as an etch mask and a contact hole 605 is formed.
Next, as shown in FIG. ID, the photo resist 607 is removed and metal films 609 and 610, which become wirings, are deposited into the contact hole 605 and the wiring groove 608 as well as on the interlayer insulation film 606. Finally, the metal films 609 and 610 are removed by CMP (Chemical Mechanical Etching) or dry etching. The metal film 610 is left within the contact hole 605 and the wiring groove 608 so that the metal film 610 is flush with the interlayer insulation film 606, thereby completing an embedded wiring consisting of the metal films 609 and 610.
According to the embedded wiring formation method using the above-stated dual damascene process, however, since the interlayer insulation film 602 is etched with the interlayer nitride film 603 used as a mask, it is necessary not to complete etching the interlayer nitride film 603 before the contact hole 605 penetrating the interlayer insulation film 602 is formed. For that reason, the interlayer nitride film 603 has to be formed thick. If the interlayer nitride film 603 is made thicker, however, the interlayer nitride film 603 covered with the interlayer insulation film 606 remains thick to disadvantageously increase inter-wiring capacity. In other words, a plasma oxide film is normally used as an interlayer insulation film. The dielectric constant of the nitride film is higher than that of the plasma oxide film. The thickness of the interlayer insulation film needs to be constant in light of the necessity of leak characteristics and the like. As a result, if the thickness of the nitride film which replace the oxide film is large, i.e., if the ratio of the nitride film to the insulating film is high, inter-wiring capacity increases due to the thick nitride film.
If the inter-wiring capacity increases, the problem of signal delay occurs, thereby disadvantageously hampering the recent demand to provide a higher-speed semiconductor device.